The present invention relates generally to semiconductor memory systems and in particular t a segmented non-volatile memory array having multiple sources so that blocks of the array can be erased separately and having improved source line decode circuitry.
Non-volatile semiconductor memory systems have become increasingly popular, including flash memory systems. FIG. 1 is a simplified diagram of the cross-section of a typical flash memory cell 10. Cell 10 is an N-channel device formed in a P-type substrate 12. An N-type drain region 14 is formed in substrate 12 as is an N-type source region 16. Source region 16 includes an N-type region 16A formed in the substrate 12 having a an N+-type region 16B formed inside region 16A so as to form a graded source region 16.
The drain and regions source 14 and 16 are spaced apart from one another so as to form a channel region 12A in the substrate intermediate the two regions. A floating gate 18 is disposed above the channel region 12A and a control gate 20 is disposed above the floating gate 18. The floating gate is separated from the channel region 12A by a thin (100 xc3x85) gate oxide layer 22. The floating and control gates 18 and 20 are typically both formed from doped poly silicon. The control gate 20 is separated from the floating gate 18 by an interpoly dielectric layer 24. Other than being capacitively coupled to other elements of cell 10, the floating gate 18 is electrically isolated from the rest of the cell.
Table 1 below shows typical conditions for performing program, read and erase operations (two approaches) on flash cell 10.
If cell 10 is in an erased state, the cell will have a threshold voltage, called an erased threshold voltage, which is typically approximately +2 volts. If the cell is in a programmed state, the cell will have a programmed threshold voltage of typically approximately +6 volts. In a read operation, the control-gate-to-source voltage of the cell is +5 volts as can be seen from Table 1, above. The drain 14 will be connected to a small positive voltage of typically +1.5 volts and the source 16 is grounded. Thus, if the cell 10 is in a programmed state, the cell will not conduct current in the read operation since the gate-to-source voltage of +5 volts is less than the programmed threshold voltage of +6 volts. If the cell is in an erased state, the gate to source voltage will exceed the erased threshold voltage so that the cell will conduct current. The presence or absence of cell current in a read operation is detected by a sense amplifier so that the state of the cell can be determined.
In order to program the flash cell 10, Table 1 indicates that the source 16 is grounded and the drain 14 is connected to +6 volts. The control gate 20 is connected to a high voltage such as +12 volts. The combination of conditions will cause electrons to travel from the source 16 towards the drain 14. Some of these electrons will possess sufficient energy to pass through the gate oxide 22 towards the positive voltage on the control gate 20. Those electrons, sometimes referred to as hot electrons, will be deposited on the floating gate 18 and will remain there until the cell 10 is erased. The presence of electrons on the floating gate 18 will tend to increase the threshold voltage of the cell, as previously noted.
Table 1 depicts two approaches for erasing a cell. The first approach (Erase 1), a cell is erased by floating the drain 14 and applying a large positive voltage, such as +12 volts, to the source 16. The control gate 20 is grounded. This combination causes electrons stored on the floating gate 18 to pass through the thin gate oxide 22 and to be transferred to the source 16. The physical mechanism for the transfer is commonly referred to as Fowler Nordheim tunneling.
The above conditions for erasing a cell (Erase 1) have been viewed by others as disadvantageous in that the large positive voltage (+12 volts) applied to the source region is difficult to implement in an actual memory system. First, the primary supply voltage VCC in a typical integrated circuit memory system is +5 volts and is provided by an external power supply such as a battery. Thus, one approach would be to include a charge pump on the memory integrated circuit which is also powered by the primary supply voltage VCC. However, a typical integrated circuit memory system may include a million or more cells all or a very large group of which will be erased at the same time. Thus, the charge pump circuit must be capable of providing-relatively large amounts of current on the order of 20 to 30 milliamperes. This has been viewed by others as impractical thus necessitating the use of an a second external supply voltage for producing the +12 volts applied to the source region. This would typically preclude battery powered operation where multiple batteries, such as a +5 volt primary supply battery and a +12 volts battery, is not practical.
The application of the relatively high voltage of +12 volts has also been viewed as disadvantageous in that there was believed to be a tendency to produce high energy holes (xe2x80x9chotxe2x80x9d holes) at the surface of the source region 16 near the channel region 12a. These positive charges were said to have a tendency to become trapped in the thin gate oxide 20 and eventually migrate to the floating gate and slowly neutralize any negative charge placed on the floating gate during programming. Thus, over time, the programmed state of the cell may be altered. Other deleterious effects due to the presence of holes have been noted, including the undesired tendency to program non-selected cells.
The above-described disadvantages of the erase conditions set forth in Table 1 (Erase 1) have been noted in U.S. Pat. No. 5,077,691 entitled FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION. The solution in U.S. Pat. No. 5,077,691 is summarized in Table 1 (Erase 2). A relatively large negative voltage ranging from xe2x88x9210 to xe2x88x9217 volts is applied to the gate 22 during an erase operation. In addition, the primary supply voltage VCC of +5 volts (or less) is applied to the source region 16. The drain region 14 is left floating.
Although the source current remains relatively high, the voltage applied to the source is sufficiently low that the +5 volt primary supply voltage VCC can be used directly or the source voltage may be derived from the primary supply voltage using a series regulator or a resistive divider in combination with a buffer circuit. In either event, since the source voltage is equal to or less than the primary supply voltage, the large source currents required in erase operations can be provided without the use of charge pump circuitry. The high impedance control gate 20 of the flash cell draws very little current. Accordingly, the large negative voltage applied to the control gate 20 in the erase operation can be provided by a charge pump circuit. Thus, according to U.S. Pat. No. 5,077,691, only a single external power supply, the +5 volt supply for VCC, need be used.
In a flash memory system, the flash cells 10 are arranged in a cell array which typically includes several rows and several columns of cells. Each of the rows has an associated word line connected to the control gate 20 of the cells 10 located in the row. Each of the columns has an associate bit line connected to the drain 14 of each cell located in the column. The sources 16 of all of the cells of the array are usually connected in common, but as will be explained, the sources may be separately connected.
FIG. 2A is a simplified plan view of a conventional layout of a pair of flash cells 10A and 10B of a cell array. FIG. 2B is a schematic diagram of cells 10A and 10B of FIG. 2A. As can be seen in FIG. 2B, cells 10A and 10B have their respective sources connected in common. Typically, the two sources are actually a single source region shared by the two cells 10A and 10B. Cells 10A and 10B are located in a common array column and in separated rows. The column has an associated bit line BL0 which is connected to the drains of cells 10A and 10B. Cell 10A is in a row having an associated word line WL0 connected to its control gate 20 and cell 10B is in an adjacent row having its control gate 20 connected to an associated word line WL1.
The bit lines, including bit line BL0, extend vertically along the array and include an underlying diffusion component 26A of doped semiconductor material and an overlying metal line component 26B. The metal line component 26B makes electrical contact with the diffusion component 26A every two cells 10 by way of contacts 28. The source lines have a horizontal segment SLD0 which runs generally parallel to the word lines and is made of doped semiconductor material. The source lines also have a vertical segment SLM0 which runs generally parallel to the bit lines and is formed from metal. The horizontal and vertical components SLD0 and SLM0 are electrically connected by way of a contact 30 located at the intersection of the two segments every two rows of the array.
Cell 10A has its control gate 20 connected to horizontal word line WL0, a doped polysilicon line which extends across the array. Cell 10B has its control gate 20 connected to horizontal word line WL1 which also extends across the array. A flash cell (10A, 10B) is formed at the intersection of the each of the word lines and bit lines.
FIG. 3A is a simplified plan view of the layout of a relatively small conventional flash cell array 32 and FIG. 3B is a schematic diagram of the FIG. 3A array. Array 32 is comprised of twelve rows, each having an associated horizontal polysilicon word line WL0-WL11. The array also has twelve columns, with each column having an associated metal bit line BL0-BL11. Array 32 also includes four vertical metal source lines SLM0-SLM3 which are connected in common to the six horizontal diffused source lines SLD0-SLD5. Each metal source line SLMN is connected to the diffused source lines SLDN every two rows. The metal source lines SLM are spaced every four columns. For example, adjacent metal source lines SLM0 and SLM1 are separated by four bit lines BL0-BL3.
The metal source lines SLM0-SLM3 are electrically connected together by circuitry (not depicted) external to array 32. Thus, all of the source lines of the array are nominally at the same electrical potential. However, the horizontal diffused source lines SLD0-SLD5 have a relatively high resistance, in comparison to the metal source lines. This high resistance can have an adverse impact upon memory operations, particularly programming and reading operations. The use of multiple metal source lines functions to reduce the overall source line resistance. However, each metal line occupies a significant amount of integrated circuit area so that the use of multiple metal source lines will increase the die area and thereby effectively increase the cost of manufacturing the cell array.
Flash memory systems are typically erased in bulk. That means that either all or a large part of the array are erased at the same time. By way of example, the entire array 32 of FIGS. 3A and 3B would be erased in a single operation. As indicated by Table 1, this can be accomplished by applying +12 volts to the common source lines SLM0-SLM3, grounding all of the word lines WLN0-WLN11 and floating all of the bit lines BL0-BL11.
There exist conventional memory arrays which provide the capability of erasing less than the entire array. This feature is particularly useful in many memory applications where it is desirable to retain some data stored in the memory while erasing and then reprogramming other data in the memory. The capability of erasing less than the entire memory is typically accomplished by electrically isolating the source lines of individual blocks of the memory array. A particular block is erased by applying a high voltage, such as +12 volts (Table 1) to the source line associated with the block being erased The word lines of the block to be erased are grounded and the bit lines of the block are left floating. As is known, the word lines and source lines of the erase blocks not being erased, the deselected erase blocks, are grounded so that the cells in the deselected erase blocks are not erased.
In large memory arrays, there is an increased likelihood that one or more cells will be defective. There exists various techniques to correct or otherwise compensate for such defective cells so that the memory will continue to be functional. However, there are certain cell failure mechanisms that interfere with the operation of the remainder of the memory and thereby effectively prevent proper memory operation. This is especially true in memory arrays having separate erase blocks where a cell failure in one block may prevent proper operation of the remaining erase blocks.
The present invention is particularly applicable to large memory arrays having separate erase blocks. The large arrays can contain cells with certain failure modes which would ordinarily prevent proper operation of conventional memories, but which do not prevent operation of a memory using an array in accordance with the present invention. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
An arrangement of flash memory cells including a plurality of erase blocks is disclosed. The erase blocks each include flash memory cells arranged into an array of rows and columns, with the cells in a column connected to bit lines common to each erase block and with the cells in a row connected to a common word line. Each of the erase blocks has either a single common source line or a group of common source lines.
The arrangement further includes a source line decoder circuit comprising a separate control transistor associated with each of the common source lines, with the control transistor having an input terminal connected to the associated source line and an output terminal connected to a common global source line and a control terminal for receiving a control signal that causes the transistor to switch between a conductive and non-conductive state. When a cell of a selected erase block is being read, programmed or erased, the control transistors associated with the other or deselected erase blocks are switched to the non-conductive state so that the associated source line will be at a high impedance level. The high impedance level will reduce the possibility that a defective cell present in one of the deselected erase blocks will interfere with the operation of the selected erase block.